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IS42G32256
IS42G32256
256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
ISSI
GRAPHIC FEATURES
* SMRS cycle - Load mask register - Load color register * Write per bit (old mask) * Block write (eight columns)
ISSI(R)
(R)
ADVANCE INFORMATION SEPTEMBER 1998
FEATURES
* 256,144 words x 32 bits x 2-bank organization * All inputs are sampled at the positive going edge of the system clock * Dual internal bank control * Single 3.3V 3V power supply * Programmable mode register - Burst length (1, 2, 4, 8, and full page) - CAS latency (2 and 3) - Burst type: Sequential and Interleave * Burst Read single-bit Write Operation * Refresh capability - Auto, self-refresh * 2,048 refresh cycles/32 ms * LVTTL compatible inputs and outputs * 100-pin PQFP (14mm x 20mm)
DESCRIPTION
The ISSI IS42G32256 is a high-speed 16-Mbit CMOS Synchronous Graphics RAM organized as 256K words x 32 bits x 2 banks. With SGRAM, all input and output signals are synchronized with the rising edge of the system clock. Programmable Mode Register and Special Registers provide a choice of Read or Write burst lengths of 1, 2, 4, or 8 locations or a Full Page with burst termination options. The SGRAM performance is enhanced with the Write-per-bit (WPB) and eight columns of Block Write functions. The IS42G32256 is ideal for high-performance, highbandwidth applications including workstation graphics, set top box, games, and PC-2D/3D graphic applications.
Table 1. Key Timing Parameters Symbol tCK Parameter Clock Cycle Time Access Time @ CL = 3 Operating Frequency -7 7 6 143 -8 8 6.5 125 -10 10 7 100 Units ns ns MHz
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
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IS42G32256
ISSI
DQM0-3 MASK REGISTER BLOCK WRITE CONTROL LOGIC WRITE CONTROL LOGIC
MASK
(R)
MUX
COLOR REGISTER
DATA IN BUFFER DQ31-DQ0
COLUMN MASK
DATA OUT BUFFER
LATENCY & BURST LENGTH
CLK CKE CS RAS CAS WE DSF DQM0-3
SENSE AMPLIFIER
PROGRAM REGISTER
TIMING REGISTER
COLUMN DECODER
256K x 32 MEMORY CELL ARRAY
256K x 32 MEMORY CELL ARRAY
DQM0-3
ROW DECODER
SERIAL COUNTER
REFRESH COUNTER
ROW ADDRESS BUFFER
COLUMN ADDRESS BUFFER
INPUT REGISTER
CLOCK
A0-A10
Figure 1. IS42G32256 Functional Block Diagram
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Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
IS42G32256
ISSI
(R)
DQ3 VCCQ DQ4 DQ5 GNDQ DQ6 DQ7 VCCQ DQ16 DQ17 GNDQ DQ18 DQ19 VCCQ VCC GND DQ20 DQ21 GNDQ DQ22 DQ23 VCCQ DQM0 DQM2
WE CAS RAS CS
BA (A10) A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A0 A1 A2 A3 VCC NC NC NC NC NC NC NC NC NC NC GND A4 A5 A6 A7
DQ2 GNDQ DQ1 DQ0 VCC NC NC NC NC NC NC NC NC NC NC GND DQ31 DQ30 GNDQ DQ29
DQ28 VCCQ DQ27 DQ26 GNDQ DQ25 DQ24 VCCQ DQ15 DQ14 GNDQ DQ13 DQ12 VCCQ GND VCC DQ11 DQ10 GNDQ DQ9 DQ8 VCCQ NC DQM3 DQM1 CLK CKE DSF NC A9
Figure 2. IS42G32256 Pin Configuration, 100-pin PQFP
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IS42G32256
Table 2. Pin Descriptions Symbol A0-A9 Pin Number 30-34, 47-51 I/O I
ISSI
(R)
A10/BP
29
I
CAS
CKE
26
I
54
I
CLK
55 28
I I
CS
DQ0-DQ31
DQM0-DQM3
1, 3-4, 6-7, 9-10, 12-13, 17-18, 20-21, 60-61, 63-64, 68-69, 71-72, 74-75, 77-78, 81-81, 83-84, 97-98, 100 23-24, 56-57
I/O
Name and Function Address: Row/Column addresses are multiplexed on the same pins. Row address: RA0RA9 Column address: CA0-CA7 Bank Select Address: Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Column Address Strobe: Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Clock Enable: Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock + tCKS prior to new command. Disable input buffers for power down in standby. System Clock: Active on the positive going edge to sample all inputs. Chip Select: Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMX. Data Input/Output: Data Inputs/Outputs are multiplexed on the same pins.
I/O
DSF
53 27 I
RAS WE
VCCQ Vcc GNDQ GND NC
25 2, 8, 14, 22, 59, 67, 73, 76, 79 15, 35, 65, 96 5, 11, 19, 62, 70, 82, 99 16, 46, 66, 85 36-45, 52, 58, 86-95
I
Data Input/Output Mask: Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte Masking) Define Special Function: Enables write per bit, block write and special mode register set. Row Address Strobe: Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access and precharge. Write Enable: Enables write operation and row precharge. Supplies voltage for data output Power Supply Voltage Ground for DQ Ground No connect
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IS42G32256
Table 3. Frequency vs. AC Parameter Relationships IS42G32256: 7 ns (Unit: number of clocks)
ISSI
CAS
tRC 63 ns 9 8 7 6 5 5 tRAS 42 ns 6 6 5 4 4 3 tRP 21 ns 3 3 3 2 2 2 tRRD 14 ns 2 2 2 2 2 1 tRCD 20 ns 3 3 2 2 2 2 tCCD 7 ns 1 1 1 1 1 1 tCDL 7 ns 1 1 1 1 1 1 tRDL 7 ns 1 1 1 1 1 1
(R)
Frequency 143 MHz (7 ns) 125 MHz (8 ns) 100 MHz (10 ns) 83 MHz (12 ns) 75 MHz (13.4 ns) 66 MHz (15 ns)
Latency 3 3 2 2 2 2
IS42G32256: 8 ns (Unit: number of clocks)
CAS
Frequency 125 MHz (8 ns) 100 MHz (10 ns) 83 MHz (12 ns) 75 MHz (13.4 ns) 66 MHz (15 ns) 50 MHz (20 ns) Latency 3 3 2 2 2 2
tRC 70 ns 9 8 6 6 5 4
tRAS 48 ns 6 5 4 4 4 3
tRP 24 ns 3 3 2 2 2 2
tRRD 16 ns 2 2 2 2 2 1
tRCD 20 ns 3 2 2 2 2 1
tCCD 8 ns 1 1 1 1 1 1
tCDL 8 ns 1 1 1 1 1 1
tRDL 8 ns 1 1 1 1 1 1
IS42G32256: 10 ns (Unit: number of clocks)
CAS
Frequency 100 MHz (10 ns) 83 MHz (12 ns) 71 MHz (14 ns) 66 MHz (15 ns) 50 MHz (20 ns) 40 MHz (25 ns) Latency 3 3 2 2 2 2
tRC 80 ns 8 7 6 6 4 4
tRAS 50 ns 5 5 4 4 3 2
tRP 26 ns 3 3 2 2 2 2
tRRD 20 ns 2 2 2 2 1 1
tRCD 20 ns 2 2 2 2 1 1
tCCD 10 ns 2 2 2 2 1 1
tCDL 10 ns 1 1 1 1 1 1
tRDL 10 ns 1 1 1 1 1 1
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IS42G32256
Table 4. Truth Table
Function Mode Register Set(2,3) Special Mode Register Set(2,3,8) Auto Refresh(4) Self Refresh, Entry(4) Self Refresh, Exit(4) Bank Active/Row Address Write Per Bit Disable(5,6) Bank Active/Row Address Write Per Bit Enable(5,6,10) Read and Column Address Auto Precharge Disable(5) Read and Column Address Auto Precharge Enable(5,6) Write and Column Address Auto Precharge Disable(5,6) Write and Column Address Auto Precharge Enable(5,6,7,10) Block Write and Column Address Auto Precharge Disable(5,6) Block Write and Column Address Auto Precharge Enable(5,6,7,10) Burst Stop(8) Precharge Bank Selection Precharge Both Banks Clock Suspend or Active Power Down Entry Clock Suspend or Active Power Down Exit Precharge Pover Down Mode Entry Precharge Pover Down Mode Exit DQM(9) No Operation Command CKEn-1 H H H H L L H H H H H H H H H H H H H L H H L L H H H CKEn X X H L H H X X X X X X X X X X X L L H L L H H X X X
ISSI
CS
L L L L L H L L L L L L L L L L L L H X L H L H X L H
(R)
RAS
L L L L H X L L H H H H H H H L L H X X H X V X X H X
CAS
L L L L H X H H L L L L L L H H H H X X H X V X X H X
WE
L L H H H X H H H H L L L L L L L H X X H X V X X H X
DSF L H L L X X L H L L L L H H L L L X X X X X V X X X X
DQM X X X X X X X X X X X X X X X X X X X X X X X X V X X
A10 A9 A8-A0 OP CODE OP CODE X X X X X X X X X X X X V Row Address V Row Address V L Column Address V H Column Address V L Column Address V H Column Address V L Column Address V H Column Address X X X V L X X H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Notes: 1. V = Valid, X = Don't Care, H = Logic High, L = Logic Low 2. OP Code: Operand Code; A0-A10: Program keys (@MRS); A5, A6: LMR or LCR select. (@SMRS) Color register exists only one per DQi which both banks share. So does Mask Register. Color or mask is loaded into chip through DQ pin. 3. MRS can be issued only at both banks precharge state. SMRS can be issued only if DQs are idle. A new command can be issued at the next clock of MRS/SMRS. 4. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/Self refresh can be issued only at both precharge state. 5. A10: bank select address. If "Low" at read, (block) write, row active and precharge, bank A is selected. If "High" at read, (block) write, row active and precharge, bank B is selected. If A9 is "High" at row precharge, A10 is ignored and both banks are precharged. 6. It is determined at row active cycle whether normal/block write operates in write per bit mode or not. For A bank write, at A bank row active, for B bank write, at B bank row active. Terminology: Write per bit = I/O mask. (Block) Write with write per bit mode = masked (block) write. 7. During burst read or write with auto precharge, new read/(block) write command cannot be issued. Another bank read/(block) write command can be issued at tRP after the end of burst. 8. Burst stop command is valid only at full page burst length. 9. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (write DQM latency is 0) but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2.) 10. Graphic features added to SDRAMs original features. If SDF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQs.
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IS42G32256
Table 5. SGRAM vs SDRAM SDRAM Function DSF SGRAM Function MRS L MRS H SMRS Bank Active L Bank Active with Write per bit Disable H Bank Active with Write per bit Enable Write
ISSI
(R)
L H Normal Block Write Write
Notes: 1. If DSF is low, SGRAM functionality is identical to SDRAM functionality. 2. SGRAM can be used as a unified memory by the appropriate DSF control; SGRAM = Graphic Memory + Main Memory.
Table 6. Mode Register Field Table to Program Modes Register Programmed with MRS Address Function Test Mode A8 A7 0 0 1 1 A9 0 1 0 1 0 1 Type Mode Register Set Vendor Use Only Length Burst Single Bit A6 0 0 0 0 1 1 1 1 A10 RFU
(1)
A9 W.B.L.
(2)
A8, A7 TM
A6, A5, A4 CAS Latency Burst Type A3 0 1 Type Sequential Interleave 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
A3 BT
A2, A1, A0 Burst Length
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved -- 2 3 Reserved Reserved Reserved Reserved
Burst Length A2 A1 A0 0 1 0 1 0 1 0 BT=0 1 2 4 8 Reserved Reserved Reserved
(3)
BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
Write Burst Length
1 256(Full)
Special mode Register Programmed with SMRS Address Function A10, A9, A8, A7 X A6 LC
(4)
A5 LM
(4)
A4, A3, A2, A1, A0 X
Load Color A6 Function 0 Disable 1 Enable
Load Mask A5 Function 0 Disable 1 Enable
Notes: 1. RFU (Reserved for Future Use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 3. The full column burst (256-bit) is available only at Sequential mode of burst type. 4. If LC and LM both high (1), data of mask and color register will be unknown.
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain DKE = "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s. 3. Issue precharge commands for all banks of the devices. 4. Issue two or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Sequence of 4 and 5 may be changed. The device is now ready for normal operation.
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IS42G32256
Table 7. Burst Sequence (Burst Length = 4) Initial Address A1 A0 0 0 l 1 0 l 0 1 0 1 2 3 Sequential 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 Interleave 1 0 3 2 2 3 0 1 3 2 1 0
ISSI
(R)
Table 8. Burst Sequence (Burst Length = 8) Initial Address A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Table 10. Pixel to DQ Mapping (at Block Write) Column Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 3 Byte I/O31-I/O24 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 2 Byte I/O23-I/O16 DQ 16 DQ 17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 1 Byte I/O15-I/O8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ 15 0 Byte I/O7-I/O0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
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IS42G32256
DEVICE OPERATIONS Clock (CLK)
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and Icc specifications.
ISSI
(R)
burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE, DSF and all the address inputs are ignored.
Power-up
The following sequence is recommended for Power-up: 1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the condition at the inputs before or along with VDD (and VDDQ) supply. The clock signal must also be asserted at the same time. 2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition. 3. Both banks must be precharged now. 4. Perform a minimum of two auto refresh cycles to stabilize the internal circuitry. 5. Perform a Mode Register Set cycle to program the CAS latency, burst length and burst type as the default value of mode register is undefined. At the end of one clock cycle from the mode register set cycle, the device is ready for operation. When the above sequence is used for Power-up, all the outputs will be in high-impedance state. The highimpedance of outputs is not guaranteed in any other power-up sequence. Note: Sequence of 4 and 5 may be changed.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SGRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SGRAM enters the power down mode from the next clock cycle. The SGRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "tSS+lCLOCK" before the high going edge of the clock, then the SGRAM becomes active from the same clock edge accepting all the input commands.
Bank Select (A10)
This SGRAM is organized as two independent banks of 262,144 words x 32 bits memory arrays. The A10 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. When A10 is asserted low, bank A is selected. When A10 is latched high, bank B is selected. The banks select Al0 is latched at bank activate, read, write, mode register set and precharge operations.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of SGRAM. It programs the CAS latency, burst type, addressing, burst length, test mode and various vendor specific options to make SGRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SGRAM. The mode register is written by asserting low on CS, RAS, CAS, WE and DSF (The SGRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0-A9 and A10 in the same cycle as CS, RAS, CAS, WE and DSF going low is the data written in the mode register. One clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0-A2, burst type
Address Inputs (A0-A9)
The 18 address bits are required to decode the 262,144 word locations are multiplexed into ten address input pins (A0-A9). The 10-bit row address is latched along with RAS and A10 during bank activate command. The 8-bit column address is latched along with CAS, WE and A10 during read or with command. When RAS, CAS and WE are high, The SGRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate,
NOP and Device Deselect
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IS42G32256
uses A3, CAS latency (read latency from column address) A4-A6, A7-A8 and A10 are uses for vendor specific options or test mode use. And the write burst length is programmed using A9. A7-A8 and A10 must be set to low for normal SGRAM operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
ISSI
(R)
goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid for all burst length.
Bank Activate
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD (min) is the internal timing parameter of SGRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the next higher integer. The SGRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SGRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min). Every SGRAM bank activate command must satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max). The number of cycles for both tRAS (min) and tRAS (max) can be calculated similar to tRCD specification.
Burst Write
The burst write command is similar to burst read command, and is used to write data into the SGRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The write burst can also be terminated by using DQM for blocking data and precharging the bank "tRDL" after the last data input to be written into the active row. See DQM Operation also.
DQM Operation
The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SGRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. DQM is also used for device selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. DQM masks the DQs by a byte regardless that the corresponding DQs are in a state of WPB masking or Pixel masking. Please refer to DQM timing diagram also.
Burst Read
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and RAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output
Precharge
The precharge is performed on an active bank by asserting low on CS, RAS, WE and A9 with valid A10 of the bank to be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfy from the bank activate command in the desired bank. "tRP" is defined as the minimum time required to precharge a bank.
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The minimum number of clock cycles required to complete row precharge is calculated by dividing "tRP" with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank has to be precharged within tRAS (max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
ISSI
(R)
refresh is the preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6 s or the burst of 2048 auto refresh cycles in 32 ms.
Self Refresh
The self refresh is another refresh mode available in the SGRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SGRAM. In self refresh mode, the SGRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRC before the SGRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting self refresh.
Auto Precharge
The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy tRAS (min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A9. If burst read or burst write command is issued with low on A9, the bank is left active until a new command is asserted. Once auto precharge command is given, no new command are possible to that particular bank until the bank achieves idle state.
Both Banks Precharge
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS and WE with high on A9 after all banks have satisfied tRAS (min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, all banks are in idle state.
Define Special Function (DSF)
The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions as 256K x 32 x 2 Bank SGRAM. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode can be entered only by setting DSF high when issuing commands which otherwise would be normal SGRAM commands. SGRAM functions such as RAS Active, Write and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR respectively that DSF controls.
Auto Refresh
The storage cells of SGRAM need to be refreshed every 32 ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRC (min). The minimum number of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOPs until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto
Special Mode Register Set (SMRS)
There are two kinds of special mode registers in SGRAM. One is color register and the other is mask register. Those usage will be explained at "Write Per Bit" and "Block Write" session. When A5 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low, load color register is filled with color data for associated DQ's through the DQ pins. If both A5 and A6 are high at SMRS, data of mask and color cycle is required to complete the write in the mask register and the color register at LMR and LCR respectively. The next color of LMR and LCR, a new commands can be
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issued. SMRS, compared with MRS, can be issued at the active state under the condition that DQs are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can be obtained by referring corresponding timing diagram.
ISSI
(R)
If write per bit was disabled by a bank active command with DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking during normal write operations, except that the control is extended to the consecutive eight columns of the block write.
Write Per Bit
Write per bit (i.e., I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when enable. Bank active command with DSF=High enable write per bit for the associated bank. The mask used for write per bit operations is stored in the mask register accessed by SWCBR (Special Mode Register Set Command). When a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enable for the bank being written. No additional timing conditions. Write per bit writes can be either masking is the same for write per bit and non-WPB write.
CLK CKE CS RAS CAS WE DSF 2 CLK BW Figure 3. Timing Diagram to Illustrate tBWC. (2CLK Clcle Block Write) HIGH
Block Write
Block write is a feature allowing the simultaneous writing of consecutive eight columns of data within a RAM device during a single access cycle. During block write the data to be written comes from the internal "color" register and DQ I/O pins are used for independent column selection. The block of column to be written is aligned on 8-column boundaries and is defined by the column address with the three LSBs ignored. Write command with DSF=1 enable block write for the associated bank. The block width is eight columns where column ="n" bits for by "n" part. The color register is the same width as the data port of the chip. It is width via a SWCBR where data present on the DQ pins is to be coupled into the internal color register. The color register provides the data masked by the DQ column select, WPB mask (if enable), and DQM byte mask. Column data masking (Pixel masking) is provided on an individual column basis for each byte of data. The column mask is driven on the DQ pins during a block write command. The DQ column mask function is segmented on a per bit basis (i.e., DQ[0:7] provided the column mask for data bits [0:7], DQ[8:15] provided the column mask for data bits [8:15], DQ0 masks column [0] for data bits [0:7], DQ9 masks column [1] for data bits [8:15], etc.). Block writes are always non-burst independent of the burst length that has been programmed into to the mode register. If write per bit was enabled by the bank active command with DSF=1, then write per bit masking of the color register data is enabled.
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Table 11. Summary of SGRAM Basic Features and Benefits Features Interface 256K x 32 x 2 SGRAM Synchronous Benefits
ISSI
(R)
Better interaction between memory and system without waitstate of asynchronous DRAM. High speed vertical and horizontal drawing. High operation frequency allows performance gain for SCROLL, FILL, and BitBLT. Pseudo-infinite row length by on-chip interleaving operation. Hidden row activation precharge. High-speed vertical and horizontal drawing. High speed vertical and horizontal drawing. Programmable burst of 1, 2, 4, 8 and full page transfer per column address. Programmable burst of 1, 2, 4, 8 and full page transfer per column address. Switch to burst length of 1 at write without MRS. Compatible with Intel and Motorola CPU based system. Programmable CAS latency. High speed FILL, CLEAR, Text with color registers. Maximum 32-byte data transfer (e.g., for 8bpp: 32 pixels) with plane and byte masking functions. A and B bank share. Write-per-bit capability (bit plane masking). A and B bank share. Byte masking (pixel masking for 8bpp system) for data-out/in. Each bit of the mask register directly controls a corresponding bit plane. Byte masking (pixel masking for 8bpp system) for color DQi.
Bank Page Depth /1 Row Total Page Depth Burst Length (Read) Burst Length (Write)
2 each 256 bit 2048 bytes 1, 2, 4, 8 Full Page 1 2 4 8 Full Page BRSW
Burst Type CAS Latency Block Write
Sequential & Interleave 2, 3 8-Column
Color Register Mask Register
1 each 1 each DQM0-3
Mask function
Write per bit Pixel Mask at Block Write
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BASIC FEATURES AND FUNCTION DESCRIPTION
1. CLOCK SUSPENDED DURING WRITE (BURST LENGTH = 4) 2. CLOCK SUSPENDED DURING READ (BURST LENGTH = 4)
ISSI
(R)
CLK COMMAND CKE INTERNAL CLK DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
D0 D0 D1 D1 D2 D2
NOT WRITTEN
WR
RD
MASKED BY CKE
MASKED BY CKE
D3 D3
Q0
Q1 Q0 Q1
Q2 Q2
Q3 Q3
SUSPENDED DOUT
Note: 1. CKE to CLK disable/enable = 1 clock.
Figure 4. Clock Suspend
1. WRITE MASK (BURST LENGTH = 4)
2. READ MASK (BURST LENGTH = 4)
CLK COMMAND DQM
MASKED BY CKE MASKED BY CKE
WR
RD
DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
D0 D0
D1 D1
D3
Q0
HI-Z HI-Z
Q2 Q1
Q3 Q2 Q3
DQM TO DATA IN MASK = 0 CLK
DQM TO DATA OUT MASK = 2
3. DQM WITH CLOCK SUSPEND (FULL PAGE READ) NOTE 2
CLK COMMAND CKE DQM DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
Q0 HI-Z HI-Z Q2 Q1 HI-Z HI-Z Q4 Q3 HI-Z HI-Z Q6 Q5 Q7 Q6 Q8 Q7 RD
Notes: 1. There are four DQMi (i = 0-3). Each DQMi masks eight DQs. (One Byte, one Pixel for 8bpp.) 2. DQM masks data out Hi-Z after two clocks which should be masked by CKE "L".
Figure 5. DQM Operation
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IS42G32256
ISSI
(R)
1. READ INTERRUPTED BY READ (BURST LENGTH = 4) (SEE NOTE 1.)
CLK COMMAND ADD DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
t CCD
(SEE NOTE 2)
RD A
RD B QA0 QB0 QA0 QB1 QB0 QB2 QB1 QB3 QB2 QB3
2. WRITE INTERRUPTED BY (BLOCK) WRITE (BURST LENGTH = 2)
3. WRITE INTERRUPTED BY READ (BURST LENGTH = 2)
CLK COMMAND ADD DQ
WR WR WR BW WR RD
t CCD (NOTE 2) A DA0 t CDL (NOTE 3) 4. BLOCK WRITE TO BLOCK WRITE B DB0 DB1
t CCD (NOTE 2) A DC0 B
(NOTE 4)
t CCD (NOTE 2) A B DB0 DB1 DB0 DB1
PIXEL
t CDL (NOTE 3
DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
DA0 DA0 t CDL (NOTE 3)
CLK COMMAND ADD DQ
BW NOP
(NOTE 7)
BW
A PIXEL t BWC (NOTE 6)
X
B PIXEL
Notes: 1. By "Interrpt", it is possible to stop burst read/write by external before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access; read, write, and block write. 2. tCCD: CAS to CAS delay (=1CLK). 3. tCDL: Last data in to new column address delay (=1CLK). 4. Pixel: Pixel mask. 5. tCC: Clock cycle time. 6. tBWC: Block write minimum cycle time. 7. Other bank can be active or precharge.
Figure 6. CAS Interrupt (I)
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IS42G32256
1. CLOCK LATENCY = 2, BURST LENGTH = 4.
CLK CMD 1 DQM DQ CMD 2 DQM DQ CMD 3 DQM DQ CMD 4 DQM DQ
Q0
(NOTE 1) HI-Z HI-Z HI-Z
ISSI
(R)
RD
RD
D0 RD
D1 WR
D2
D3
D0
D1 WR
D2
D3
RD
D0
D1 WR
D2
D3
RD
D0
D1
D2
D3
2. CLOCK LATENCY = 3, BURST LENGTH = 4.
CLK CMD 1 DQM DQ CMD 2 DQM DQ CMD 3 DQM DQ CMD 4 DQM DQ CMD 5 DQM DQ
Q0
HI-Z (NOTE 2)
RD
WR
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
Q0 RD
HI-Z
D0
D1 WR
D2
D3
D0
D1
D2
D3
Notes: 1. To prevent bus contention, there should be at least one gap between data in and data out. 2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Figure 7. CAS Interrupt (II): Read Interrupted by Write and DQM 16
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IS42G32256
CLK
(NOTE 2)
ISSI
(R)
COMMAND DQM DQ
WR
WR
(NOTE 1)
D0
D1
D2
D3
MASKED BY DQM
Notes: 1. To Inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation.
Figure 8. Write Interrupted by Precharge and DQM
1. NORMAL WRITE (BURST LENGTH = 4)
CLK COMMAND DQ
WR D0 D1 D2 D3 t RDL (NOTE 1) PRE
2. BLOCK WRITE
BW PIXEL t BPL (NOTE 1)
PRE
3. READ (BURST LENGTH = 4)
CLK COMMAND DQ (CLOCK LATENCY = 2 DQ (CLOCK LATENCY = 3
WR Q0 Q1 Q0 PRE
(NOTE 2)
1
Q2 Q1
Q3
2
Q2
Q3
Notes: 1. tRDL: Write data-in to PRE command delay, tBPL: Block Write data-in to PRE command delay. 2. Number of valid output data after row precharge: 1, 2 for CAS, Latency = 2, 3 respectively.
Figure 9. Precharge
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IS42G32256
1. NORMAL WRITE (BURST LENGTH = 4)
CLK COMMAND DQ
WR D0 D1 D2 D3
(NOTE 1)
ISSI
2. BLOCK WRITE
(R)
BW PIXEL t BPL
AUTO PRECHARGE STARTS
t RP t BAL
(NOTE 1)
AUTO PRECHARGE STARTS
3. READ (BURST LENGTH = 4)
CLK COMMAND DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
RD Q0 Q1 Q0 Q2 Q1
(NOTE 1)
Q3 Q2 Q3
AUTO PRECHARGE STARTS
Note: 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
Figure 10. Auto Precharge
1. WRITE INTERRUPTED BY PRECHARGE (BURST LENGTH = 4)
CLK COMMAND DQM DQ
D0 D1 D2 D3 t RDL (NOTE 1) WR PRE
2. WRITE BURST STOP (FULL PAGE ONLY)
CLK COMMAND
WR STOP
DQ
D0
D1
D2 t BDL
3. READ INTERRUPTED BY PRECHARGE (BURST LENGTH = 4)
CLK COMMAND DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
RD PRE
NOTE 3
4. READ BURST STOP (FULL PAGE ONLY)
CLK COMMAND
RD STOP
NOTE 3
Q0
Q1 Q0
1 2
Q1
DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3)
Q0
Q1 Q0
1 2
Q1
Figure 11. Burst Stop and Precharge Interrupted
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IS42G32256
1. MODE REGISTER SET
CLK
(NOTE 4)
ISSI
2. SPECIAL MODE REGISTER SET
CLK
PRE t RP MRS
1 CLK
(R)
COMMAND
ACT
COMMAND
SMRS
1 CLK
ACT
SMRS
1 CLK
SMRS
1 CLK
ACT
1 CLK
Notes: 1. tRDL: 1 CLK; last data in to Row Precharge. 2. tBDL: 1 CLK; last data in to Burst Stop Delay. 3. Number of valid output data after Row Precharge or Burst Stop: 1, 2 for CAS, Latency = 2, 3 respectively. 4. PRE: Both banks precharge, if necessary. MRS can be issued only at all banks precharge state.
Figure 12. MRS and SMRS
1. CLOCK SUSPEND (=ACTIVE POWER DOWN) EXIT
CLK CKE INTERNAL CLK CMD
t SS
(NOTE 1)
2. POWER DOWN (=PRECHARGE POWER DOWN) EXIT
CLK CKE INTERNAL CLK
t SS
(NOTE 2)
RD
CMD
NOP
ACT
Figure 13. Clock Suspend Exit and Power Down Exit
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IS42G32256
1. AUTO REFRESH (NOTE 3)
CLK
(NOTE 4) (NOTE 5)
ISSI
(R)
CMD CKE
PRE
AR
CMD
t RP
t RC
2. SELF REFRESH (NOTE 6)
CLK
(NOTE 4)
CMD CKE
PRE
SR
CMD
t RP
t RC
Notes: 1. Active power down: one or more banks active state. 2. Precharge power down: both banks precharge state. 3. The Auto Refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command. During tRC from Auto Refresh command, any other command can not be accepted. 4. Before excuting auto/self refresh command, both banks must be idle state. 5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs except CKE will be "Don't Care", and outputs will be in Hi-Z state. During tRC from self refresh exit command, any other comman can not be accepted. Before/after self refresh mode, burst auto refresh (2K cycles) is recommended.
Figure 14. Auto Refresh and Self Refresh
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Table 11. About Burst Type Control Basic Mode Sequential Counting Interleave Counting Pseudo-Mode Pseudo-Document Sequential Counting At MRS, A3="0". See the Burst Sequence Table. (BL=4, 8) BL=1, 2, 4, 8 and full page wrap around.
ISSI
(R)
At MRS A3="1". See the Burst Sequence Table. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting At MRS A3="1". (See to interleave Counting Mode) Staring Address LSB 3 bits A 0-2 should be "000" or "111". @BL=8 -- if LSB ="000": Increment Counting. -- if LSB ="111": Decrement Counting. For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8) -- @ write, LSB ="000", Accessed Column in order 0-1-2-3-4-5-6-7 -- @ read, LSB ="111", Accessed Column in order 7-6-5-4-3-2-1-0 At BL=4, same applications are possible. As above example, at interleave Counting mode, by confining starting address to some value, Pseudo-Decrement Counting Mode can be realize. See the Burst Sequence Table carefully. At MRS A3="0". (See to Sequential Counting Mode) A0-2 ="111". (See to Full Page Mode). Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized. -- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8) -- @ Pseudo-Binary Counting Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command) Note: The next column address of 256 is 0. Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Pseudo-Binary Counting
Random Mode
Random Column Access, tCCD = 1 CLK
Table 12. About Burst Length Control Basic Mode 1 2 4 8 Full Page Special Mode BRSW Block Write At MRS A2, 1, 0 = "000". At auto precharge, tRAS should not be violated. At MRS A2, 1, 0 = "001". At auto precharge, tRAS should not be violated. At MRS A2, 1, 0 ="010". At MRS A2, 1, 0 ="011". At MRS A2, 1, 0 ="111". Wrap around mode (infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt. At MRS A9 ="1". Read Burst =1, 2, 4, 8, full page/write Burst =1. At auto precharge of write, tRAS should not be violated. 8-Column Block Write. LSB A0-2 are ignored. Burst length =1. tRAS should not be violated. At auto precharge, tRAS should not be violated. tBDL =1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively. Using burst stop command, random mode it is possible only at full page burst length. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL =1 with DQM, valid DQ after burst stop is 1, 2 for CL=2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read write burst with auto precharge, CAS interrupt can not be issued.
Random Mode
Burst Stop
Interrupt Mode
RAS Interrupt CAS Interrupts
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Table 13. Mask Function Procedure 1. Normal Write I/O masking: By Mask at Write Per Bit Mode, the selected bit planes keep the original data. If bit plane 0, 3, 7, 9, 19, 22, 24, and 31 keep the original value. a. STEP I. SMRS(LMR): Load mask [31-0]="0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110" II. Row Active with DSF "H": Write Per Bit Mode Enable III. Perform Normal Write b. Illustration I/O (=DQ) External Data-in DQMi Mask Register Before Write After Write 31 24 11111111 DQM3=0 01111110 00000000 01111110 23 16 11111111 DQM2=0 10110111 00000000 10110111 15 8 00000000 DQM1=0 11111101 11111111 00000010 7 0 00000000 DQM0=1 01110110 11111111 11111111
ISSI
(R)
DQM byte masking 2. Block Write Pixel masking: By Pixel Data issued through DQ pin, the selected pixels keep the original data. See Pixel To DQ Mapping Table. If Pixel 0, 4, 9, 13, 18, 22, 27, and 31 keep the original white color. Assume 8bpp White = "0000, 0000", Red = "1010, 0011", Green = "1110, 0001", Yellow = "0000, 1111", Blue = "1100, 0011" a. STEP I. SMRS(LCR): Load color (for 8bpp, through x32 DQ color0-3 are loaded into color registers). Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red) "1100,0011,1110,0001,0000,1111,1010,0011" II. Row Active with DSF "L": I/O Mask by Write Per Bit Mode Disable III. Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"
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Table 13. Mask Function Procedure (continued) b. Illustration I/O (=DQ)(1) 31 24 DQMi DQM3=0 Color Register Color3=Blue Before Block Write & DQ (Pixel data) 000 White DQ24=H 001 White DQ25=H 010 White DQ26=H 011 White DQ27=L 100 White DQ28=H 101 White DQ29=H 110 White DQ30=H 111 White DQ31=L After Block Write 000 Blue 001 Blue 010 Blue 011 White 100 Blue 101 Blue 110 Blue 111 White 23 16 DQM2=0 Color2=Green White DQ16=H White DQ17=H White DQ18=L White DQ19=H White DQ20=H White DQ21=H White DQ22=L White DQ23=H Green Green White Green Green Green White Green 15 8 DQM1=0 Color1=Yellow White DQ8=H White DQ9=L White DQ10=H White DQ11=H White DQ12=H White DQ13=L White DQ14=H White DQ15=H Yellow White Yellow Yellow Yellow White Yellow Yellow
ISSI
(R)
7 0 DQM0= 1 Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White
Note: 1. At normal write, ONE column is selected among columns decoded by A2-0 (000-111). At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
3. Pixel and I/O masking: By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See Pixel To DQ Mapping Table. Assume 8bpp, White = "0000, 0000", Red = "1010, 0011", Green = "1110, 0001", Yellow = "0000, 1111", Blue = ` 1100, 0011" a. STEP I. SMRS(LCR): Load color (for 8bpp, through x 32 DQ color0-3 are loaded into color registers) Load (color3, color2, color1, color0, ) = (Blue, Green, Yellow, Red) ="1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011" II. SMRS(LMR) Load mask. Mask[31-0] = "1111, 1111, 1101, 1101, 0100, 0010, 0111, 0110" Byte 3 : No I/O Masking ; Byte 2: I/O Masking ; Byte 1: I/O and Pixel Masking ; Byte 0: DQM Byte Masking III. Row Active with DSF "H" : I/O mask by Write Per Bit Mode Enable IV. Block Write with DQ [31-0] = "0111, 0111,1111, 1111, 0101, 0101, 1110, 1110" (Pixel Mask)
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Table 13. Mask Function Procedure (continued) b. Illustration I/O (=DQ)(1) Color Register DQMi Mask Register Before Write After Write 31 24 23 16 15 Yellow 00001111 DQM1=0 01000010 Green 11100001 Red 10100011 8 7
ISSI
(R)
0
Blue 11000011 DQM3=0 11111111 Yellow 00001111 Blue 11000011
Green 11100001 DQM2=0 11011101 Yellow 00001111 Blue 11000011
Red 10100011 DQM0=1 01110110 White 00000000 White 00000000
I/O (=DQ)(1) 31 24 DQMi DQM3=0 Color Register Color3=Blue Before Block Write & DQ (Pixel data) 000 Yellow DQ24=H 001 Yellow DQ25=H 010 Yellow DQ26=H 011 Yellow DQ27=L 100 Yellow DQ28=H 101 Yellow DQ29=H 110 Yellow DQ30=H 111 Yellow DQ31=L After Block Write 000 Blue 001 Blue 010 Blue
011 Yellow Blue Green White
23 16 DQM2=0 Color2=Green Yellow DQ16=H Yellow DQ17=H Yellow DQ18=H Yellow DQ19=H Yellow DQ20=H Yellow DQ21=H Yellow DQ22=H Yellow DQ23=H Blue Blue Blue Blue Blue Blue Blue
15 8 DQM1=0 Color1=Yellow Green DQ8=H Green DQ9=L Green DQ10=H Green DQ11=L Green DQ12=H Green DQ13=L Green DQ14=H Green DQ15=L Red Green Red Red Green Red Green
7 0 DQM0=1 Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White
100 101 110 111
Blue Blue Blue Yellow
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
Note: 1. DQM byte masking. 2. At normal write, ONE column is selected among columns decoded by A2-0 (000-111). At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
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Table 14. Function Truth Table Current State IDLE
ISSI
DSF X X X X L H L H L H L H X X X L H L H X L H X L H X X L H L H L H X L H X BA (A10) X X X BA BA BA X BA X BA ADDR Action NOP NOP ILLEGAL(2) ILLEGAL(2) Row Active; Latch Row Address; Non-I/O Mask Row Active; Latch Row Address; I/O Mask Auto Refresh or Self Refresh(4) NOP Auto Refresh or Self Refresh(5) ILLEGAL Mode Register Access(5) Special Mode Register Access(6) NOP NOP ILLEGAL(2) Begin Read; Latch CA; Determine AP ILLEGAL Begin Write; Latch CA; Determine AP Begin Write; Latch CA; Determine AP ILLEGAL(2) Precharge ILLEGAL ILLEGAL ILLEGAL Special Mode Register Access(6) NOP (Continue Burst to End * Row Active) NOP (Continue Burst to End * Row Active) Term burst Row active ILLEGAL Term burst, Begin Read; Latch CA; Determine AP(3) ILLEGAL Term burst, Begin Write; Latch CA; Determine AP(3) Term burst. Begin Write; Latch CA; Determine AP(3) ILLEGAL(2) Term Burst, Precharge timing for Reads(3) ILLEGAL ILLEGAL
(R)
CS RAS CAS WE
H L L L L L L L L L L L H L L L L L L L L L L L L H L L L L L L L L L L L X H H H L L L L L L L L X H H H H H H L L L L L L X H H H H H H H L L L L X H H L H H H H L L L L X H H L L L L H H H L L L X H H H L L L L H H H L X_ H L X H H L L H H L L X H L H H L L H L L H L L X H L L H H L L H L. L X
Row Active
Read
X X X CA RA RA PA X X X OP Code OP Code X X X X X X BA CA, AP X X BA CA, AP BA CA, AP BA RA BA RA X X X X X X OP Code X X X X X X X X BA CA,AP X X BA CA, AP BA CA, AP BA RA BA PA X X X X
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IS42G32256
Table 14. Function Truth Table (continued) Current State Write
ISSI
DSF X X L H L H L H X L H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BA (A10) X X X X BA X BA BA BA BA X X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X ADDR X X X X CA, AP X CA, AP CA, AP RA RA X X X X X CA, AP CA, AP RA, PA X X X X CA, AP CA, AP RA, PA X X X X CA, AP RA PA X X X X CA, AP RA PA X Action NOP (Continue Burst to End * Row Active) NOP (Continue Burst to End * Row Active) Term burst * Row Active ILLEGAL Term burst, Begin Read; Latch CA; Determine AP(3) ILLEGAL Term burst, Begin Write; Latch CA; Determine AP(3) Term burst, Begin Write; Latch CA; Determine AP(3) ILLEGAL(2) Term Burst: Precharge timing for Writes(3) ILLEGAL ILLEGAL NOP (Continue Burst to End Precharge) NOP (Continue Burst to End Precharge) ILLEGAL ILLEGAL(2) ILLEGAL(2) ILLEGAL ILLEGAL(2) NOP (Continue Burst to End Precharge) NOP (Continue Burst to End Precharge) ILLEGAL ILLEGAL(2) ILLEGAL(2) ILLEGAL ILLEGAL(2) NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL(2) ILLEGAL(2) NOP Idle after tRP(2) ILLEGAL(4) NOP Row Active after tBWC NOP Row Active after tBWC ILLEGAL ILLEGAL(2) ILLEGAL(2) Term Block Write: Precharge timing for Block Write(2) ILLEGAL(2)
(R)
CS RAS CAS WE
X H H H H H H H L L L L X H H H H L L X H H H H L L X H H H L L L X H H H L L L X H H H L L L L H H H L X H H L L H L X H H L L H L X H H L H H L X H H L H H L X H L L H H L L H L H X X H L H L X X X H L H L X X X H L X H L X X H L X H L X
H L L L L L L L L L L L Read H with L Auto L Precharge L L L L Write H with L Auto L Precharge L L L L PreH charging L L L L L L Block H Write L Recovering L L L L L
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Table 14. Function Truth Table (continued) Current State Row Activating
ISSI
DSF X X X X X X X X X X X X BA (A10) X X X BA BA BA X X X X X X ADDR X X X CA,AP RA PA X X X X X X Action NOP Row Active after tRCD NOP Row Active after tRCD ILLEGAL(2) ILLEGAL(2) ILLEGAL(2) ILLEGAL(2) ILLEGAL(2) NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL PA = Precharge All (A9) AP = Auto Precharge (A9)
(R)
CS RAS CAS WE
X H H H L L L X H H L L X H H L H H L X H L H L X H L X H L X X X X X X
H L L L L L L Refreshing H L L L L
Abbreviations: RA = Row Address (A0-A9) NOP = No Operation Command
BA = Bank Address (A10) CA = Column Address (A0-A7)
Notes: 1. All entries assume the CKE was active (High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA). 5. Illegal if any bank is not idle. 6. Legal only if all banks are in idle or row active state.
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Table 15. Function Truth Table for CKE Current State Self Refresh H X X X L H H X L H L H L H L H L H L H L H L L L L X X Both Bank Precharge Power Down H X X X L H H X L H L H L H L H L H L H L H L L L L X X All Banks Idle H H X X H L H X H L L H H L L H H L L H H L L L H L L L H L L L L L X X Any State Other Than Listed Above H H X X H L X X L H X X L L X X Abbreviations: ABI = All Banks Idle X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh * * * after tRC(1) Exit Self Refresh * * * after tRC(1) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down ABI(2) Exit Power Down ABI(2) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table 14 Enter Power Down(3) Enter Power Down(3) ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 14 Begin Clock Suspend next cycle(4) Exit Clock Suspend next cycle(4) Maintain Clock Suspend CKE CKE (n-1) n
ISSI
CS RAS CAS WE
DSF ADDR Action
(R)
Notes: 1. After CKEs low-to-high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKEs low-to-high transition to issue a new command. 2. CKE low to high transition is asynchronous as if restart internal clock. A minimum setup time "tSS + one clock" must be satisfy before any command other than exit. 3. Power down and self refresh can be entered only from the all banks idle state. 4. Must be a legal command.
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Table 16. Absolute Maximun Ratings(1) Symbol VCC MAX VCCQ MAX VIN VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Storage Temperature Rating -1.0 to +4.6 -1.0 to +4.6 -1.0 to +4.6 -1.0 to +4.6 1 50 0 to +70 -55 to +150 Unit V V V V W mA C C
ISSI
(R)
Table 17. DC Recommended Operating Conditions(2) (At TA = 0 to +70C) Symbol VCC, VCCQ VIH VIL Parameter Supply Voltage Input High Voltage Input Low Voltage Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 Vcc + 0.3 +0.8 Unit V V V
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. VIH (max) = 5.5V for pulse width 5 ns. 4. VIL (min) = 1.5V for pulse width 5 ns.
Table 18. Capacitance Characteristics (At TA = 0 to +25C, VCC = VCCQ = 3.3V 0.3V, f = 1 MHz) Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: A0-A10 Input Capacitance: CLK, CKE, CS, RAS, CAS, WE, DSF, DQM0-3 Data Input/Output Capacitance: DQ0-DQ31 Typ. -- -- -- Max. 4 4 5 Unit pF pF pF
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Table 19. DC Electrical Characteristics (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter IIL IOL VOH VOL ICC1 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Operating Current(1,2) Test Condition 0V < VIN < VCC, with pins other than the tested pin at 0V Output is disabled 0V < VOUT < VCC IOUT = -2 mA IOUT = +2 mA One Bank Operation, Burst Length=1 tRC tRC (min), IOL = 0 mA tCK tCK (min) CKE VIL (max) CKE VIH (min) CKE VIL (max) CKE VIH (min) tCK = tCK (min) IOL = 0 mA All banks activated tCK = tCK (min) tCK = tCK = tCK (min) tCK = tCK = tCK (min) tCK = tCK = tCK (min) tCK = -7 -8 -10 Speed Min. -5 -5 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -7 -8 -10 -7 -8 -10 -7 -8 -10 IOL = 0 mA, tBWC (min) -7 -8 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5 5 -- 0.4 145 180 170 3 2 30 15 3 2 50 30 195 170 140 195 170 140 195 170 140 2 190 180 170
ISSI
Unit A A V V mA
(R)
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Active Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current (In Burst Mode)(1)
mA mA mA mA mA
CAS latency = 3 CAS latency = 2
mA
ICC5
Auto-Refresh Current
tRC = tRC (min)
mA
ICC6 ICC7
Self-Refresh Current Operating Current (one Bank Block Write)
CKE 0.2V tRC tRC (min)
mA mA
Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 F should be inserted between Vcc and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
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Table 20. AC Characteristics(1,2,3) Symbol
tCK tAC tCHI tCL tOH
ISSI
-7 Min. Max. -8 Min. Max.
8 -- 12 -- -- 6.5 -- 8 3 -- 3 -- 2.5 -- 2.5 -- 2.5 -- 0 -- 4 8 4 12 2.5 -- 1 -- 2.5 -- 1 -- 2.5 -- 1 -- 1CLK+3 -- 2.5 -- 1 -- 72 -- 48 102,000 24 -- 20 -- 16 -- 16 -- 16 -- 40 -- 40 -- 16 16 1 -- -- -- 30 32
(R)
Parameter
Clock Cycle Time
-10 Min. Max.
10 -- 13 -- -- 7 -- 9 3.5 -- 3.5 -- 2.5 -- 2.5 -- 2.5 -- 0 -- 4 10 4 14 3 -- 1 -- 3 -- 1 -- 3 -- 1 -- 1CLK+3 -- 3 -- 1 -- 90 -- 50 102,000 26 -- 20 -- 20 -- 20 -- 20 -- 50 -- 50 -- 20 20 1 -- -- -- 30 32
Units
ns ns ns ns ns
tLZ tHZ tDS tDH tAS tAH tCKS tCKH tCKA tCS tCH tRC tRAS tRP tRCD tRRD tDPL tDAL
tBDPL tBWC tT tREF
7 -- 10 -- Access Time From CLK(4) -- 6 -- 7 CLK HIGH Level Width 2.5 -- CLK LOW Level Width 2.5 -- Output Data Hold Time CAS Latency = 3 2.5 -- CAS Latency = 2 2.5 -- CAS Latency = 1 2.5 -- Output LOW Impedance Time 0 -- Output HIGH Impedance Time(5) CAS Latency = 3 4 6 CAS Latency = 2 4 10 Input Data Setup Time 2 -- Input Data Hold Time 1 -- Address Setup Time 2 -- Address Hold Time 1 -- CKE Setup Time 2 -- CKE Hold Time 1 -- CKE to CLK Recovery Delay Time 1CLK+3 -- Command Setup Time (CS, RAS, CAS, WE, DQM, DSF) 2 -- Command Hold Time (CS, RAS, CAS, WE, DQM, DSF) 1 -- Command Period (REF to REF / ACT to ACT) 63 -- Command Period (ACT to PRE) 45 100,000 Command Period (PRE to ACT) 21 -- CAS to RAS Delay 20 -- Command Period (ACT [0] to ACT[1]) 14 -- Last Data In To Precharge CAS Latency = 3 14 -- Command Delay Time CAS Latency = 2 14 -- Last Data In To Active / Refresh CAS Latency = 3 35 -- Command Delay time CAS Latency = 2 35 -- (Auto-Precharge, same bank) Block Write to Precharge Command Delay Time 14 -- Block Write Cycle Time 14 -- Transition Time 1 30 Refresh Cycle Time -- 32
CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns ns ns ns
Notes: 1. When power is first applied, memory operation should be started 100 s after Vcc and VccQ reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. 3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.). 4. Access time is measured at 1.4V with the load shown in the figure below. 5. The time tHZ (max.) is defined as the time required for the output voltage to transition by 200 mV from VOH (min.) or VOL (max.) when the output is in the high impedance state.
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Figure 21. Operating Frequency / Latency Relationships Symbol CL tCK -- tCAC tRCD tRAC tRC tRAS tRP tRRD tCCD tDPL tDAL tRBD tWBD tRQL tWDL tBDAL tEP tSMCD tRR tPQL tQMD tDMD tMCD Parameter Clock Cycle Time Operating Frequency CAS Latency Active Command to Read/Write Command Delay Time RAS Latency (tRCD + tCAC) Command Period (REF to REF/ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT[0] to ACT [1]) Column Command Delay Time (READ, READA, WRIT, WRITA) Last Data In to Precharge Command Delay Time Last Data In to Active/Refresh Command Delay Time (Auto-Precharge, Same Bank) Burst Stop Command to Output in HIGH-Z Delay Time (Read) Burst Stop Command to Input in Invalid Delay Time (Write) Precharge Command to Output in HIGH-Z Delay Time (Read) Precharge Command to Input in Invalid Delay Time (Write) Block Write to Active Command (Auto Precharge, Same Bank) Last Data Out to Precharge Command Special Mode Register Set to Command Register Set Command to Register Set Command Last Output to Auto-Precharge Start Time (Read) DQM to Output Delay Time (Read) DQM to Input Delay Time (Write) Mode Register Set to Command Delay Time -7 3 2 7 10 143 100 3 2 3 2 6 4 9 6 6 4 3 2 2 2 1 1 2 5 3 0 3 0 6 -2 1 2 -2 2 0 1 2 4 2 0 2 0 5 -1 1 2 -1 2 0 1 -8 3 2 8 12 125 83 3 2 3 2 6 4 9 6 6 4 3 2 3 2 1 1 2 5 3 0 3 0 6 -2 1 2 -2 2 0 1 2 4 2 0 2 0 5 -1 1 2 -1 2 0 1 -10 3 2 10 15 100 66 3 2 3 2 6 4 9 6 6 4 3 2 2 3 1 1 2 5 3 0 3 0 6 -2 1 2 -2 2 0 1 2 4 2 0 2 0 5 -1 1 2 -1 2 0 1
ISSI
Units ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
(R)
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AC TIMING WAVEFORMS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS
tRP tRC
HIGH LEVEL IS NECESSARY
RAS
CAS
A0-A8
KEY
Ra
A10/BA
KEY
BS
A9
KEY
Ra
WE
DSF
DQM DQ
HIGH LEVEL IS NECESSARY
HIGH-Z
PRECHARGE (ALL BANKS)
AUTO REREFRESH
AUTO REREFRESH
MODE REGISTER SET
ROW ACTIVE (WRITE PER BIT ENABLE OR DISABLE) : DON'T CARE
Figure 18. Power On Sequence and Auto Refresh
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IS42G32256
ISSI
t CH
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
0
1
CLK
t CC t CL t RAS
NOTE 1
CKE
HIGH
t RC t SH t RP
CS
t SH
t RCD
t SS
RAS
t SS t SH t CCD
CAS
t SH t SS Ra t SS
NOTE 2 NOTE 3
t SH Cb t SS
NOTE 3 NOTE 4 NOTE 2
A0-A8
Ca
Cb
Rb
A10
BS
BS
NOTE 3
BS
NOTE 3
BS
BS
BS
NOTE 3 NOTE 4
A9
Ra t SH
Rb
WE
NOTE 5
t SH
t SS
NOTE 6 NOTE 5
DSF
t SS t SS t SH
DQM
t RAC t SH t SAC t SLZ Qa Db t SS
WRITE OR BLOCK WRITE READ PRECHARGE ROW ACTIVE (WRITE PER BIT ENABLE OR DISABLE)
DQ
Qc
ROW ACTIVE (WRITE PER BIT ENABLE OR DISABLE)
READ
: DON'T CARE
Figure 19. Single Bit Read-Write-Read Cycle (Same Page) at CAS Latency = 3, Burst Length = 1
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Notes: 1. All inputs can be "Don't Care" when CS is high at the CLK high going edge. 2. Bank active and read/write are controlled by A10. A10 Active and Read/Write 0 Bank A 1 Bank B 3. Enable and disable auto precharge function are controlled by A9 in read/write command. A9 A10 Operation 0 0 Disable auto precharge, leave bank A active at end of burst. 0 1 Disable auto precharge, leave bank B active at end of burst. 1 0 Enable auto precharge, precharge bank A at end of burst. 1 1 Enable auto precharge, precharge bank B at end of burst. 4. A9 and A10 control bank precharge when precharge command is asserted. A9 A10 Precharge 0 0 Bank A 0 1 Bank B 1 X Both Bank 5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command. A10 DSF Operation 0 L Bank A row active, disable write per bit function for bank A. 0 H Bank A row active, enable write per bit function for bank A. 1 L Bank B row active, disable write per bit function for bank B. 1 H Bank B row active, enable write per bit function for bank B. 6. Block write/normal write is controlled by DSF. DSF Operation Minimum cycle time
ISSI
(R)
L H
Normal write Block write
tCCD tBWC
Figure 19. Single Bit Read-Write-Read Cycle (Same Page) at CAS Latency = 3, Burst Length = 1 (continued)
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ISSI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
0
CLK CKE CS
tRP
HIGH
NOTE 1
tRC
RAS
NOTE 2
CAS
A0-A8
Ra
Ca0
Rb
Cb0
A10
A9
Ra
Rb
WE
NOTE 2
DSF
DQM
t QH
DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
Qa0 t RAC
NOTE 3
Qa1
Qa2
Qa3
NOTE 4
Db0 t SHZ
Db1
Db2
Db3 t RDL
t SAC t RAC
NOTE 3
t QH Qa0 t SAC Qa1 Qa2
Qa3
NOTE 4
Db0 t SHZ
Db1
Db2
Db3 t RDL
ROW ACTIVE (A-BANK)
READ (A-BANK)
PRECHARGE (A-BANK)
ROW ACTIVE (A-BANK)
WRITE (A-BANK)
PRECHARGE (A-BANK) : DON'T CARE
Notes: 1. Minimum cycle time is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Length = 1] valid output data available after Row enters precharge. Last valid output will be Hi-Z after tSHZ from the clock. 3. Access time from Row address. tCC x (tRCD = CAS Latency = 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, and 8). At Full page bit burst, burst is wrap-around.
Figure 20. Read and Write Cycle at Same Bank at Burst Length = 4
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS
tRP
HIGH
RAS
NOTE 2
CAS
A0-A8
Ra
Ca0
Cb0
Cc0
Cd0
A10
A9
Ra tCLD tRDL
WE
NOTE 2
DSF
NOTE 1 NOTE 3
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
ROW ACTIVE (A-BANK)
READ (A-BANK)
READ (A-BANK)
WRITE (A-BANK)
WRITE (A-BANK)
PRECHARGE (A-BANK)
: DON'T CARE
Notes: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
Figure 21. Page Read and Write Cycle Same Bank at Burst Length = 4
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ISSI
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
0
1
CLK CKE CS RAS
HIGH
CAS
NOTE 4
A0-A8
RAa
CAa
CAb
RBa
CBa
CBb
A10
A9
Ra
RBa
WE
DSF
NOTE 2
tCLD
DQM
NOTE 3 NOTE 1
DQ
Pixel Mask
Pixel Mask
Pixel Mask
Pixel Mask
ROW ACTIVE WITH WRITE-PER-BIT ENABLE (A-BANK)
MASKED BLOCK WRITE (A-BANK)
MASKED BLOCK WRITE WITH AUTO PRECHARGE (A-BANK)
ROW ACTIVE (B-BANK)
BLOCK WRITE (B-BANK)
BLOCK WRITE WITH AUTO PRECHARGE (B-BANK)
: DON'T CARE
Notes: 1. Column Mask (DQi = L: Mask, DQi = H: Non-mask). 2. tBWC: Block Write Cycle time. 3. At Block Write, second cycle should be in NOP. Other Bank can be active or precharge. 4. At Block Write, CA0-2 are ignored.
Figure 22. Block Write Cycle (with Auto Precharge)
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
NOTE 1
A0-A2 A3,A4, A7,A8 A5
RAa
RBa
CBa
RAa
CAa
RBa
CBa
RAa
CAa
RAa
CBa
A6
RAa
CAa
RAa
CBa
A9
RAa
RBa
A9
WE
DSF
DQM DQ
I/O Mask Pixel Mask Pixel Mask
Color
Color
DBa0 DBa1 DBa2 DBa3
LOAD COLOR REGISTER
LOAD MASK REGISTER
MASKED BLOCK WRITE (A-BANK)
LOAD MASK REGISTER ROW ACTIVE LOAD WITH COLOR WRITE-PER-BIT REGISTER ENABLE (B-BANK)
MASK WRITE WITH AUTO PRECHARGE (B-BANK)
ROW ACTIVE WITH WRITE-PER-BIT ENABLE (A-BANK)
: DON'T CARE
Note: 1. At the next clock of special mode register set command, new command is possible.
Figure 23. SMRS and Block/Normal Write at Burst Length = 4
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
NOTE 2
HIGH
CAS
A0-A8
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A10
A9
RAa
RBb
WE
DSF
HIGH
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
ROW ACTIVE (A-BANK)
ROW ACTIVE (B-BANK) READ (A-BANK)
READ (B-BANK)
READ (A-BANK)
READ (B-BANK)
READ (A-BANK)
PRECHARGE (A-BANK) : DON'T CARE
Notes: 1. CS can be "Don't Care" when RAS, CAS, and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Figure 24. Page Read Cycle at Different Bank at Burst Length = 4
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ISSI
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
0
1
CLK CKE CS RAS
HIGH
CAS
A0-A8
RAa
KEY
CAa
RBb
CBb
CAc
CBd
A10
A9
RAa
RBb t CDL
WE
DSF
DQM DQ
Mask DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBb2 DBb3
LOAD MASK REGISTER ROW ACTIVE WITH WRITE-PER-BIT ENABLE (A-BANK)
ROW ACTIVE (B-BANK) MASKED WRITE (A-BANK)
WRITE (B-BANK)
MASKED WRITE WITH AUTO PRECHARGE (A-BANK)
WRITE WITH AUTO PRECHARGE (B-BANK) : DON'T CARE
Figure 25. Page Write Cycle at Different Bank at Burst Length = 4
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
RAa
CAa
RBb
CBb
RAc
CAc
A10
A9
RAa
RBb
RAc t CDL
NOTE 1
WE
DSF
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
ROW ACTIVE (A-BANK)
READ (A-BANK)
ROW ACTIVE (B-BANK) PRECHARGE (A-BANK)
WRITE (B-BANK) ROW ACTIVE (A-BANK)
READ (A-BANK) : DON'T CARE
Note: 1. tCDL should be met to complete write.
Figure 26. Read and Write Cycle at Different Bank at Burst Length = 4
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
Ra
Rb
Ca
Cb
A10
A9
Ra
Rb
WE
DSF
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
ROW ACTIVE (A-BANK)
ROW ACTIVE (B-BANK) READ WITH AUTO PRECHARGE (A-BANK)
AUTO PRECHARGE START POINT (A-BANK)
WRITE WITH AUTO PRECHARGE (B-BANK)
AUTO PRECHARGE START POINT (B-BANK) : DON'T CARE
Note: 1. tRDL should be controlled to meet minimum tRAS before internal precharge start (in the case of Burst Length = 1 and 2, BRSW mode and Block write).
Figure 27. Read and Write Cycle with Auto Precharge at Burst Length = 4
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
Ra
Rb
Ca
Cb
Ra
Ca
A10
A9
Ra
Rb
Ra
WE
DSF
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
Qa0 Qa1 Qb0 Qb1 Db2 Db3 Da0 Da1
Qa0
Qa1
Qb0
Qb1
Db2
Db3
Da0
Da1
ROW ACTIVE (A-BANK)
ROW ACTIVE (B-BANK)
READ WITHOUT AUTO READ PRECHARGE WITH AUTO (B-BANK) PRECHARGE AUTO (A-BANK) PRECHARGE START POINT (A-BANK)
PRECHARGE (B-BANK)
ROW ACTIVE (A-BANK)
WRITE WITH AUTO PRECHARGE (A-BANK) : DON'T CARE
Note: 1. When Read (Write) command with auto precharge is issued at A-Bank after A and B Bank activation. -- If Read (Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at the next cycle of B Bank read command input point. -- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Figure 28. Read and Write Cycle with Auto Precharge II at Burst Length = 4
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ADVANCE INFORMATION SR037-0C 09/10/98
IS42G32256
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
Ra
Rb
Cb
Ra
A10
A9
Ra
Rb
WE
DSF
t RCD
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
NOTE 1
ROW ACTIVE (A-BANK)
READ WITH AUTO PRECHARGE (A-BANK)
READ AUTO PRECHARGE WITH AUTO START POINT PRECHARGE (B-BANK) (A-BANK) ROW ACTIVE (B-BANK)
AUTO PRECHARGE START POINT (B-BANK) : DON'T CARE
Note: 1. Any command to A Bank is not allowed in this period. tRP is determined from at auto precharge start point.
Figure 29. Read and Write Cycle with Auto Precharge *** at Burst Length = 4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
45
IS42G32256
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
RAa
CAa
CAb
A10
NOTE 1 NOTE 1
A9
Ra
WE
DSF
t RCD
DQM
NOTE 2
1 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
1 2 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
QAa0 QAa1 QAa2 QAa3 QAa4 2 QAa0 QAa1 QAa2 QAa3 QAa4
ROW ACTIVE (A-BANK)
READ (A-BANK)
BURST STOP
READ (A-BANK)
PRECHARGE (A-BANK) : DON'T CARE
Notes: 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of "Full Page Write Burst Stop Cycle". 3. Burst stop is valid at full page mode.
Figure 30. Read Interupted by Precharge Command and Read Burst Stop Cycle (at Full Page Only)
46
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
IS42G32256
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
NOTE 2
HIGH
CAS
A0-A8
RAa
CAa
RBb
CAb
RAb
CBc
CAd
A10
A9
RAa
RBb
RAc
WE
DSF
DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3
QAa0 DAb0 DAb1 DBc0 DAd0 DAd1
QAa0
DAb0 DAb1
DBc0
DAd0 DAd1
ROW ACTIVE (A-BANK)
WRITE (A-BANK) ROW ACTIVE (B-BANK) READ WITH AUTO PRECHARGE (A-BANK)
ROW ACTIVE (A-BANK)
READ (A-BANK)
PRECHARGE (A-BANK)
WRITE WITH AUTO PRECHARGE (B-BANK)
: DON'T CARE
Notes: 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command. The next cycle is also starts the precharge. 3. WPB function is also possible at BRSW mode.
Figure 32. Burst Read Single Bit Write Cycle at Burst Length = 2, BRSW
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
47
IS42G32256
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ISSI
19
(R)
CLK CKE CS RAS
HIGH
CAS
A0-A8
Ra
Ca
Cb
Cc
A10
A9
Ra
WE
DSF
NOTE 1
DQM DQ
Qa0 Qa1 Qa2 Qa3 t SHZ Qb0 Qb1 Dc0 Dc2
t SHZ
ROW ACTIVE
READ
CLOCK SUSPEND
READ READ DQM
WRITE WRITE DQM CLOCK SUSPEND : DON'T CARE
Note: 1. DQM needed to prevent bus contention.
Figure 33. Clock Suspension and DQM Operation Cycle at CAS Latency = 2, Burst Length = 4
48
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
IS42G32256
0 1 2 3 4
NOTE 2 t SS
ISSI
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
CLK CKE CS RAS
t SS NOTE 1
NOTE 3
t SS
t SS
CAS
A0-A8
Ra
Ca
A10
A9
Ra
WE
DSF
DQM DQ
Qa0 Qa1 Qa2
PRECHARGE POWER-DOWN ENTRY
ROW ACTIVE PRECHARGE POWER-DOWN EXIT ACTIVE POWERDOWN ENTRY ACTIVE POWERDOWN EXIT
READ
PRECHARGE
: DON'T CARE
Notes: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least "1CLK + tSS" prior to Row active command. 3. Cannot violate minimum refresh specification (32 ms).
Figure 34. Active/Precharge Power Down Mode at CAS Latency = 2, Burst Length = 4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
49
IS42G32256
0 1 2
NOTE 2 NOTE 1
ISSI
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(R)
CLK
NOTE 4 NOTE 3
t RCmin
NOTE 6
CKE
t SS
t SS
NOTE 5
CS RAS
NOTE 7 NOTE 7
CAS
A0-A8
A10
A9
WE
DSF
DQM DQ
HI-Z
HI-Z
SELF REFRESH ENTRY
SELF REFRESH EXIT
AUTO REFRESH : DON'T CARE
Notes: TO ENTER SELF REFRESH MODE 1. CS, RAS, and CAS with CKE should be low at the same clock cycle. 2. After one clock cycle, all the inputs including the system clock can be "Don't Care" except for CKE. 3. The device remains in the self refresh mode as long as CKE stays "Low". Once the device enters self refresh mode minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if system uses burst refresh.
Figure 35. Self Refresh Entry and Exit Cycle
50
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
IS42G32256
ISSI
2 3 4 5 6
0 1 2 3 4 5 6 7 8 9 10
(R)
0
1
CLK CKE CS
NOTE 2
CLK
HIGH
CKE CS
HIGH
t RC
RAS
NOTE 1
RAS
CAS
NOTE 3
CAS
KEY RA
A0-A8
A0-A8
WE
WE
DSF
DSF
DQM DQ
DQM DQ
HI-Z
HI-Z
MRS NEW COMMAND : DON'T CARE
AUTO REFRESH
NEW COMMAND : DON'T CARE
Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle. Notes: 1. CS, raS, CAS, and WE activation and DSF of low at the same clock with address key will set internal mode register. 2. Minimum one clock cycle should be met before new RAS activation. 3. Please refer to Mode Register Set table.
Figure 37. Auto Refresh Cycle
Figure 36. Mode Register Set Cycle
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98
51
IS42G32256
ISSI
(R)
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 143 MHz 125 MHz 100 MHz Speed (ns) Cycle Time -7 -8 -10 Order Part No. IS42G32256-7PQ IS42G32256-8PQ IS42G32256-10PQ Package PQFP PQFP PQFP
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 Email: sales@issi.com http://www.issi.com
52
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C 09/10/98

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